The advantage of polysilicon transistors for use in a CMOS static random access memory (SRAM) cells has been known for quite some time. This type of cell generally has four N channel transistors formed in the substrate with two P channel transistors formed in the second layer of polysilicon. The two P channel transistors act as loads in place of the commonly-used resistor loads. The P channel transistors reduce power consumption while also improving cell stability. These advantages can also be obtained with P channel loads formed in the substrate but there is then a significant increase in the amount of space required for the cell. Having the P channel load in the second layer of polysilicon results in a cell which is nearly the same size as a cell which uses resistor loads. Even with these strong advantages, the difficulties in actually manufacturing such P channel load SRAM cells has resulted in the cell which uses resistor loads being the cell which is by far the most commonly manufactured.
One of the problems that is inherent in the P channel load cell is that N-type regions must be connected to P-type regions without the formation of a blocking PN junction. One solution to this problem was taught in U.S. Pat. No. 4,581,623, Wang. Another problem is the integrity of the gate insulator between the first and second polysilicon layers. The gate of the polysilicon transistor is formed in the first layer of polysilicon. The source, drain, and channel are formed in the second layer of polysilicon. The gate insulator is thus the interlayer insulator between the first and second polysilicon layers. The gate insulator needs to be thin enough so that the voltage on the gate can provide enough influence on the channel to provide the desired effect. The thinner the gate insulator, however, the more critical that the insulating material be of high integrity throughout. This is achieved by growing oxide at a relatively high temperature. After the first layer of polysilicon is deposited but before the interlayer insulator is formed, the sources and drains are formed in the substrate. The interlayer insulator is then formed but the high temperature needed to form a high integrity gate will deleteriously cause excessive diffusion of the source and drain regions in the substrate which have already been formed, causing short channel effects. Thus, as a compromise, the interlayer insulator is made thicker but grown or deposited at lower temperature. Annealing of the first polysilicon layer, which requires an extra heat cycle, is also desirably done to enlarge grain size to improve the performance of the polysilicon transistor. Because the extra heat cycle also increases the diffusion of source and drain regions in the substrate, the annealing must also be compromised. The annealing done at a lower than optimum temperature results in a grain size which is smaller than could be obtained but for the temperature limitations. The thick interlayer insulator and small grain size result in a polysilicon transistor which has high leakage when it is supposed to be non-conductive and is highly resistive when it is supposed to be conductive. Thus, over processing variations, the performance of the P channel load transistors formed in the second layer of polysilicon varied so widely that the improvement over the resistive loads could not be trusted and the increased process complexity further reduced yields. Thus, the resistive load cell has remained the design of choice for commercially viable SRAM products.